1. Field of the Invention
In general, the present disclosure is directed to contact geometries in semiconductor devices of integrated circuits. The present disclosure relates to device structures with a gate silicon length that is decoupled from a transistor length and, in particular, when maintaining the transistor length.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETS), also called metal oxide semiconductor field effect transistors (MOSFETS), or simply MOS transistors. Typically, present-day integrated circuits are implemented by millions of MOS transistors which are formed on a chip having a given surface area.
In MOS transistors, a current flow through a channel formed between the source and drain of a MOS transistor is controlled via a gate which is typically disposed over the channel region, independent from whether a PMOS transistor or an NMOS transistor is considered. For controlling a MOS transistor, a voltage is applied to the gate of the transistor and current flows through the channel when the applied voltage is greater than a threshold voltage which nontrivially depends on properties of a transistor such as size, material, etc.
In efforts to build integrated circuits with a greater number of transistors and faster semiconductor devices, the trend towards ultra large scale integration (ULSI) in semiconductor technology has resulted in ICs which are ever-decreasing in size and, therefore, reducing the size of MOS transistors. In present-day semiconductor technology, the minimum feature sizes of microelectronic devices have been approaching the deep submicron regime so as to meet the demand for faster and lower power microprocessors and digital circuits and, in general, semiconductor device structures which have a higher energy efficiency. A critical dimension (CD) is generally represented by a width or length dimension of a line or space that has been identified as critical to the device under fabrication to operate properly and, furthermore, determines the device performance.
As a result, the continued increase in performance of ICs has led IC designers to push CDs to smaller scales which allow increasing the integration density of IC structures. It is easy to see that the integration density depends on the dimensions of the MOS transistors representing the core building elements of ICs. An important parameter to characterize the transistor size is represented by the contacted poly pitch (CPP), which represents a measure for a distance between a source contact and a drain contact or measures a pitch between the source and drain of a transistor. In current semiconductor technologies, the CPP has been reduced down to about 80 nm. Downscaling of the CPP was accompanied by a scaling of the CDs of gate electrodes and, in particular, of length dimensions of gate electrodes. The gate length at a technology node may be roughly estimated to be on the order of a quarter of the CPP. For instance, a CPP of 192 nm has a gate CD of roughly 49 nm, a CPP of 130 nm has a gate CD of roughly 32 nm, and a CPP of 113 nm has a gate CD of roughly 28 nm.
FIG. 1 shows a conventional semiconductor device structure during a middle-end-of-line (MEOL) fabrication process flow in which source contact structures, drain contact structures and gate electrode contact structures are formed.
FIG. 1 shows a semiconductor substrate 100 and two gate electrode structures 120 and 140 disposed on a surface of the semiconductor substrate 100. As schematically depicted in FIG. 1, source and drain regions 112, 114 and 116 are formed within the semiconductor substrate 100 adjacent to the respective gate electrode structure 120 and 140 without explicitly illustrating source and drain extensions and halo regions. The gate electrode structure 120 comprises a gate insulating layer 124, a gate electrode layer 126 and a gate silicide 164 formed above the gate electrode layer 126. A spacer structure 128 is formed at each side of the gate electrode structure 120. Accordingly, the gate electrode structure 140 comprises a gate insulating layer 144, a gate electrode layer 146 and a gate silicide 168 formed on the gate electrode layer 146. Sidewall spacers 148 are formed at each side of the gate electrode structure 140.
A length dimension of the gate electrode structure 120 is schematically represented by an arrow 122 and substantially defines the length of a channel region extending between the source and drain regions 114 and 116. Accordingly, the gate electrode structure 140 has a length dimension which is schematically represented by an arrow 142 and substantially defines the length of a channel region extending between the source and drain regions 112 and 114. A contact 160 schematically represents a contact for contacting the source and drain of a transistor structure comprising one of the gate electrode structures 120, 140. The contact is disposed on the source or drain region 114. According to the illustration in FIG. 1, a CPP is schematically depicted as a pitch between the source and drain regions 114 and 116.
At a technology node, the CPP rather represents a given quantity than a variable and, therefore, the CPP together with the channel length 122 defines the space for the contact 160 to land between two neighboring gate electrode structures 120 and 140 as may be understood from the illustration in FIG. 1. A contact geometry, such as represented in FIG. 1, may be further parameterized by two parameters, “a” and “b” as schematically depicted in FIG. 1. Herein, the parameter “b” characterizes the distance between the contact 160 and the gate electrode stack 124, 126 of the gate electrode structure 120, and the parameter “a” characterizes the distance between the contact 160 and the gate silicide 164.
With FIG. 1 at hand, the person skilled in the art will understand that a scaling of the CPP down to smaller dimensions will, first of all, result in contact geometries having smaller parameters “a” and “b”. When aiming at smaller technology nodes, several issues arise with regard to the contact geometry and which become more and more important at smaller scales.
When decreasing the channel length of a transistor, a coupling between source/drain and the channel becomes stronger, such that the threshold voltage is effectively lower for transistors with shorter gate lengths, generally being referred to as Vth roll-off. For a given CPP, the gate width (e.g., reference numeral 122 in FIG. 1) is, therefore, required to be as big as possible, leading to the requirement of the parameter “a” to become smaller. In turn, the critical dimension CD of a contact (e.g., reference numeral 160 in FIG. 1) is required to be as big as possible in order to define sufficient space for the contact (e.g., reference numeral 160 in FIG. 1) to land between two neighboring gate electrode structures (e.g., reference numerals 120 and 140 in FIG. 1). However, in any case, the parameter “a” is expected to be smaller than the parameter “b” and, in particular, the parameter “a” is critical with regard to CA-PC leakage which depends on the distance between the gate silicide (e.g., reference numeral 164 in FIG. 1) formed on a gate electrode layer (e.g., reference numeral 126 in FIG. 1) and the contact (e.g., reference numeral 160 in FIG. 1) and the contact taper angle of the contact (e.g., reference numeral 160 in FIG. 1). When increasing the parameter “a” by decreasing the CD of a contact (e.g., reference numeral 160 in FIG. 1) for a fixed gate length, the contact resistance of the contact (e.g., reference numeral 160 in FIG. 1) is increased and, therefore, transistor structures having a high contact resistance are obtained. In consequence, present-day semiconductor devices at small technology nodes increasingly suffer from increased yield loss and low device performance with a high device variability and fluctuations in device characteristics.
It is, therefore, desirable to provide contact geometries with smaller CPP and smaller parameter “a” without detrimentally affecting the performance of scaled transistors. It is further desirable to provide contact geometries which maintain a sufficiently big parameter “a” at a given technology node.
In view of the above discussion, there exists a need for methods for forming a semiconductor device and for a semiconductor device structure providing a low yield loss and a lower contact resistance, while maintaining a high device performance or even increasing the device performance with smaller device variability and fluctuations in the device characteristics.